Clock recovery from data streams containing embedded reference clock values

ABSTRACT

A method and an improved apparatus for clock recovery from data streams containing embedded reference clock values controlled clock source means includes of a controllable digital fractional divider means receiving a control value from digital comparator means and a clock input from a digital clock synthesizer means driven by a fixed oscillator means.

PRIORITY

This application claims priority from Indian Application for Patent No.1084/Del/2001, filed Oct. 30, 2001, and entitled IMPROVED CLOCK RECOVERYFROM DATA STREAMS CONTAINING EMBEDDED REFERENCE CLOCK VALUES, which isincorporated herein by reference.

TECHNICAL FIELD

This invention relates to a method and an improved apparatus for clockrecovery from data streams containing embedded reference clock valuesthat uses purely digital techniques and can be incorporated withoutmajor changes in most existing applications such as MPEG based systemssuch as set-top boxes or DVD systems.

BACKGROUND OF THE INVENTION

Many applications involving streaming data, such as streaming videocontaining embedded reference-clock information to enable clocksynchronization at the receiver. An important example of such datastreams are Motion Picture Expert Group (MPEG) data streams that providean efficient format for transmitting, receiving and storing videosignals in digital format—the MPEG data stream format includes a timingreference field called Program Clock Reference (PCR) or ElementaryStream Clock Reference (ESCR) that is embedded during the encodingprocess and serves to provide a clock synchronizing source. The PCR/ESCRfield is extracted during the receive or playback process and is used tosynchronize the receiving clock with the data stream rate therebyimplementing clock recovery. The synchronizing or clock recoveryfunction is implemented by a Digital Phase Locked Lop (DPLL).

FIG. 1 shows a typical DPLL used in an MPEG receiver application. TheMPEG encoding is performed using a reference 27 MHz clock. To facilitatethe clock recovery process at the decoder, the MPEG streams areperiodically (typically every 0.1 sec) embedded with a timing referencefield called Program Clock Reference (PCR). The PCR is generated asfollows.

The 27 MHz system clock is given to a counter. A snapshot of the counteris taken periodically (rate at which the PCR has to be sent). The valuesof the counter thus obtained are stuffed into the PCR field of the MPEGstream.

On the decoding side, the clock is recovered using the values in the PCRfield.

The PCR in the MPEG stream is extracted and is stored in the receivedPCR register (1.1). The Local PCR register (1.2) stores the values ofthe PCR generated by the VOXO (1.6). The contents of the counter (1.4)are loaded into local PCR register, and the MPEG stream with the PCRfield updates the contents of received PCR register (1.1). Thecomparator (1.3) outputs an error signal depending on the differencebetween received PCR (1.1) and the local PCR (1.2). The error signal isused to drive a controlled clock source (1.7). Within the controlledclock source (1.7) the error signal is converted into analog voltage bythe D/A converter (1.5). The analog output voltage from D/A converter(1.5) biases the VOXO (1.6) to generate the required frequency. Theactual implementation may have some blocks being implemented insoftware. For example, the compare function can be easily implemented inthe software. The D/A block may consist of a PWM generator that isprogrammed by the software and a low pass filter.

U.S. Pat. No. 5,473,385 describes a DPLL apparatus in which a subtractorgives the difference between received and locally generated PCR values.The output of the subtractor, which is the error value, is fed to adigital filter connected to the input of an accumulator. The accumulatederror values are processed by an error signal generator, which producesa frequency adjustment signal for advancing or retarding the localoscillator frequency after gating with a selected video synchronizationsignal so that the clock frequency correction is performed only duringthe vertical synch or blanking interval and the effects of thesynchronization are not visible. This technique does not permit easymodification of the characteristics of the PLL as there are noprogrammable features. Also, the dropping of clocks during the verticalsynch incurs a significant risk in obtaining jitter-free reading ofdata. Finally, the implementation of this method requires major redesignof MPEG decoder circuits used in existing systems such as set-top boxes.

U.S. Pat. No. 6,072,369 uses a phase error detector, interpolator, gaincalculator, digital-to-analog converter (DAC), voltage controlledoscillator (VCO) divider, and local PCR (LPCR) counter to generate thelocal clock signal. This scheme is implemented purely in hardware anduses analog components such as the DAC and VCO. It is thereforesensitive to noise and its characteristics are not easily modifiable.

U.S. Pat. No. 6,175,385 describes three purely digital schemes thatessentially use a fixed frequency oscillator. Clock synchronization isachieved by counting clock pulses of the fixed frequency signal andadjusting the unit for incrementing or decrementing the counted value toa predetermined value in a predetermined time according to the deviationof the fixed frequency from the reference frequency. The scheme requiresa redesign of almost all the blocks used to process MPEG information inthe majority of existing applications. Further, this process needs to beimplemented during the video-blanking interval and hence is limited toapplications where such an interval is available.

SUMMARY

An embodiment of the invention eliminates or reduces the severity ofsome of the above drawbacks by providing a completely digitalimplementation of the clock-recovery systems.

Another embodiment of the invention provides dynamically configurableloop-filter characteristics.

A further embodiment of the invention provides such an implementationwhere no major re design of the existing video information processingblocks is required.

Therefore, one embodiment of invention provides an improved apparatusfor clock recovery from data streams containing embedded reference clockvalues comprising:

-   -   clock reference storage means for storing clock reference values        received from the incoming data stream connected to, input of a        digital comparator means, the second input of which is connected        to,    -   local clock (LC) storage means for storing locally generated        clock values provided by a,    -   counter means which receives a clock signal from a controlled        clock source means controlled by the output of said digital        comparator means,    -   characterized in that said controlled clock source means        includes a controllable digital Fractional Divider means        receiving a control value from said digital comparator means and        a clock input from a digital clock synthesizer means driven by a        fixed oscillator means.

For example:

The input data stream is an MPEG data stream in which said embeddedclock reference value is either the Program Clock Reference (PCR) valueor Elementary Stream Clock Reference (ESCR) value.

The comparator means is implemented using a microcontroller.

The Digital Fractional Divider is any known Digital Fractional Divider.

The said Digital Fractional Divider is implemented as claimed in ourco-pending application, U.S. application No. [attorney reference number2110-17-3], filed Oct. 10, 2002.

The gain of said comparator means is adjusted in accordance withchanging input conditions.

The gain of said comparator is adjusted to a high value prior toobtaining a match between said local clock and said clock reference andreduced after obtaining said match.

Another embodiment of the invention is a method for enabling clockrecovery from data streams containing embedded reference clock values,comprising the steps of:

-   -   storing the received reference clock values,    -   generating a controlled local clock,    -   comparing said received reference clock with said generated        local clock;    -   adjusting said controlled local clock to match said received        reference clock;    -   characterized in that said controlled local clock is generated        by performing controlled fractional division on the output from        a fixed clock source.

The above method may also include adjusting of the loop gain inaccordance with changing input conditions, such as the loop gain isadjusted to a high value prior to lock-in and to a lower value afterlock-in.

BRIEF DESCRIPTION OF THE DRAWINGS

Embodiments of the invention will now be described with reference to theaccompanying drawings:

FIG. 1 shows a DPLL used in MPEG receiver application according to knownart;

FIG. 2 shows a circuit diagram for a preferred embodiment of theinvention; and

FIG. 3 shows the fractional divider (2.6) of FIG. 2 and its functioning,in accordance with an embodiment of the invention.

DETAILED DESCRIPTION

In the following detailed description of exemplary embodiments of theinvention, reference is made to the accompanying drawings, which form apart hereof. The detailed description and the drawings illustratespecific exemplary embodiments by which the invention may be practiced.These embodiments are described in sufficient detail to enable thoseskilled in the art to practice the invention. It is understood thatother embodiments may be utilized, and other changes may be made,without departing from the spirit or scope of the present invention. Thefollowing detailed description is therefore not to be taken in alimiting sense, and the scope of the present invention is defined by theappended claims. In some instances, well known methods, procedures,components, and circuits have not been described in detail so as not toobscure the present invention.

FIG. 1 is described in the Background.

FIG. 2 shows a preferred embodiment of the invention. The PCR/ESCR fromthe data stream is extracted and stored in the PCR register (2.1). TheLPCR register (2.2) stores the values of the PCR generated by thecontrolled clock source (2.5). On receiving a data stream with PCR/ESCRfield, the PCR register (2.1) and LPCR register (2.2) are updated byloading into them the contents of PCR/ESCR field and the counter (2.4)respectively. The comparator (2.3) is a logic circuit, which preferablyincludes a microcontroller for programmatically adjusting the loop gainin accordance with changing input conditions. In one embodiment, theloop gain is adjusted to a high value prior to obtaining a match betweensaid local clock and said clock reference, and is reduced afterobtaining said match. In another embodiment, the comparator (2.3) may beimplemented with logic hardware.

The comparator (2.3) outputs a digital error signal depending upon thedifference between PCR register (2.1) and LPCR register (2.2), which actas its inputs. The error signal may have both an integer part and afractional part. The comparator logic circuit generates the error signalin a manner so as to minimize the difference between the receivedprogram clock reference (PCR) and the locally generated PCR (LPCR),thereby providing synchronization and enabling clock recovery. By doingso, the circuit as a whole functions as a digital phase locked loop.

The fractional divider (2.6) is responsible for the clock recoveryscheme. The fractional divider could be any known fractional divider. Apreferred embodiment of the fractional divider is shown in FIG. 3 and isdescribed in co-pending U.S. patent application No. [attorney referencenumber 2110-17-3] entitled “An Improved Fractional Divider”, filed Oct.10, 2002, which is incorporated herein by reference. The fractionaldivider (2.6) receives the digital error signal comprising an integerpart and a fractional part on its configuration bus from the output ofthe comparator (2.3). The fractional divider (2.6) converts the errorsignal to the required frequency. The fractional divider (2.6) isclocked by a synthesizer (2.8), generating a high frequency clock(typically 600 MHz) with the help of a reference frequency from acrystal oscillator (2.7).

FIG. 3 shows the fractional divider (2.6) of FIG. 2, in accordance withan embodiment of the invention. The output from the synthesizer (2.8) ofFIG. 2 is given to a counter (3.1) of the fractional divider (2.6), asshown FIG. 3. The counter can be configured to divide by either n or n+1depending upon the logic-state of the carry out.

The fractional adder (3.2) is a binary adder. The fractional incrementregister (3.3) holds the fractional increment value. The contents of thefractional increment register are added to the current contents of thefractional adder when the clock enable is high and there is a risingSynth clock edge.

By way of example, to get 27 MHz clock, the reference frequency of 600MHz from the synthesizer (2.8 of FIG. 2) has to be divided by 22.222222.To achieve this, the counter (3.1) is programmed as divide by 22. Thefractional increment value register (3.3) is initialized with thefractional value viz., 0.222222. The counter (3.1) is arranged such thatwhen it completes one programmed count, the clock out completes oneclock cycle, simultaneously the contents of the fractional incrementregister (3.3) are added to the contents of fractional adder (3.2) onceevery clock out cycle. When an overflow in the fractional adder occurs,the carry out is set to logic ‘1’. This configures the counter as divideby 23. Table 1 shows the division factor and the fractional part in thefractional adder for every 27 MHz clock cycle generated.

TABLE 1 Division Fractional S. No Factor Division 1 22 0.2222222 2 220.4444444 3 22 0.6666666 4 22 0.8888888 5 23 0.1111111 6 22 0.3333333 722 0.5555556 8 22 0.7777778 9 23 0.0

The ratio of frequencies is 27:600=9:200. That implies the phases willmatch after 9 clocks of 27 MHz and 200 clocks of 600 MHz. The firstcolumn represents the number of clock cycles of the 27 MHz clock, thecontents of the second column when added is 200, which is equal to thenumber of 600 MHz clocks. The division by a factor ‘n’ or ‘n+1’ isimplemented by a programmable divider. The ‘Fractional Adder is a 24-bitbinary adder. The addition operation in the ‘Fractional Adder’ unit isperformed when ‘Adder Enable’ is high and on a rising Synth clock edge.The ‘Adder Enable’ is high for only one Synth clock cycle. The ‘CarryOut’ signal is high only when there is a carry from the addition. Thedivision logic is configured to divide by ‘n’ when carry out signal islow. It is configured to divide by ‘n+1’ when carry out signal is high.

This embodiment also relates to a method for enabling clock recoveryfrom data streams (2.9) containing embedded reference clock valueswherein a locally generated clock (2.10) is adjusted to match with thereceived embedded reference clock value, the adjustable local clockbeing generated by controlled fractional division (2.6) of the output ofa fixed clock source.

1. (canceled)
 2. A digitally implemented clock recovery apparatus forclock recovery from a data stream containing embedded reference clockvalues, the apparatus comprising: a clock reference register operable tostore clock reference values received from the incoming data stream; adigital comparator operable to compare the stored clock reference valuesand a locally generated clock reference values, and to provide a controlvalue in response; and a controlled clock source operable to provide alocally generated clock signal synchronized with the clock referencevalues in response to the control value, wherein the controlled clocksource includes a controllable digital fractional divider operable toreceive the control value and a clock input from a digital clocksynthesizer.
 3. The apparatus of claim 2, wherein the digital clocksynthesizer is driven by a fixed oscillator.
 4. The apparatus of claim2, further including a local clock reference register operable to storethe locally generated clock reference values.
 5. The apparatus of claim2, further including a counter operable to receive the locally generatedclock signal and provide the locally generated clock reference values.6. The apparatus of claim 2, wherein the gain of the comparator isadjusted in accordance with changing input conditions.
 7. The apparatusof claim 6, wherein the gain of the comparator is adjusted to a highvalue prior to obtaining a match between the controlled clock source andthe clock reference and reduced after obtaining the match.
 8. Theapparatus of claim 2, wherein the data stream comprises an MPEG datastream. 9-14. (canceled)
 14. An improved apparatus for clock recoveryfrom data streams containing embedded reference clock values comprising:clock reference storage means for storing clock reference valuesreceived from the incoming data stream connected to, input of a digitalcomparator means, the second input of which is connected to, local clock(LC) storage means for storing locally generated clock values providedby a, a counter which receives a clock signal from a controllabledigital fractional divider controlled by the output of said digitalcomparator, wherein said controllable digital fractional dividerreceives a control value from said digital comparator and a clock inputfrom a digital clock synthesizer means driven by a fixed oscillator. 15.An improved apparatus as claimed in claim 14, wherein said input datastream is an MPEG data stream in which said embedded clock referencevalue is either the program clock reference (PCR) value or elementarystream clock reference (ESCR) value.
 16. An improved apparatus asclaimed in claim 14, wherein said digital comparator means isimplemented using a microcontroller. 17.-25. (canceled)